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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16703-1E
32-bit Microcontroller
CMOS
FR60 MB91305 MB91305
DESCRIPTION
MB91305 is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O resources for embedded controllers requiring high-performance and high-speed CPU processing. The FR family is the most suitable for embedded applications, for example, DVD player, printer, TV, and PDP control, that require a high level of CPU processing power. MB91305 is an FR60 model that is based on the FR30/40 of CPUs. It has enhanced bus access and is optimized for high-speed use.
FEATURES
1. FR CPU
* 32-bit RISC, load/store architecture, 5 stages pipeline * With USB function (MOD = 0000B) : operating frequency of 64 MHz [original oscillation at 48 MHz] 48 MHz / 3-divided x 4 multiplication (Continued)
PACKAGE
176-pin plastic LQFP
(FPT-176P-M07)
Copyright(c)2006 FUJITSU LIMITED All rights reserved
MB91305
(Continued) * With no USB function (MOD = 0010B) : operating frequency of 64 MHz [original oscillation at 16 MHz] 16 MHz x 4 multiplication * 16-bit fixed-length instructions (basic instructions) , one instruction per cycle * Memory-to-memory transfer, bit processing, instructions including barrel shift, etc. : instructions appropriate for embedded applications * Function entry and exit instructions, multi load/store instructions of register contents : instructions compatible with high-level languages * Register interlock function to facilitate assembly-language coding * Built-in multiplier/instruction-level support - Signed 32-bit multiplication : 5 cycles - Signed 16-bit multiplication : 3 cycles * Interrupts (saving of PC and PS) : 6 cycles, 16 priority levels * Harvard architecture enabling simultaneous execution of both program access and data access * 4-word queues in the CPU provided to add an instruction prefetch function * Instructions compatible with the FR family
2. Bus Interface
This bus interface is used for external bus and internal macro USB function. * Maximum operating frequency of 32 MHz * 16-bit data input-output * Totally independent 8-area chip select outputs that can be defined in the minimum units of 64K bytes. The CS2 and CS3 areas are reserved as shown below. CS0, CS1, and CS4 to CS7 can be used only. - CS2 area : USB function - CS3 area : Unused * Basic bus cycle (2 cycles) * Automatic wait cycle generator that can be programmed for each area and can insert waits because CS2 and CS3 are reserved, the setting is fixed. * 24-bit address can be fully outputted * 8- and 16-bit data I/O * Prefetch buffer installed * Unused data and address pins can be used as general-purpose I/O and resource function. * Support of interfaces for various memory modules Asynchronous SRAM, asynchronous ROM/Flash memory Page-mode ROM/Flash memory (a page-size of 1, 2, 4, or 8 can be selected) Burst-mode ROM/Flash memory (MBM29BL160D/161D/162D etc.) SDRAM (or FCRAM type, CAS Latency1 to Latency8, 2/4 bank product) Address/data multiplexed bus (8-bit/16-bit width only) * Basic bus cycle : 2 cycles * Automatic wait cycle generator (Max 15 cycles) that can be programmed for each area * External wait cycles due to RDY input * Endian setting of byte ordering (big/little) Note : CS0 area is only big endian. * Write disable setting (read only area) * Enable/disable set of capturing to the built-in cache * Enable/disable set of prefetch function * External bus arbitration using BRQ and BGRNT is enabled
3. Built-in Memory
64K bytes RAM of built-in F-bus 2
MB91305
4. Instruction Cache Memory
*Instruction cache : 4K bytes *2 way set associative *128 block/way, 4 entry (4 words) /block *Lock function allows specific program codes to stay resident in cache. *Instruction RAM function : A part of the instruction cache not in use can be used as RAM for instruction execution
5. DMAC (DMA Controller)
*5 channels (channels 1 and 2 are connected to the USB function.) *3 transfer sources (internal peripherals, software) *Addressing mode with 32-bit full address specifications (increase, decrease, fixed) *Transfer modes (demand transfer, burst transfer, step transfer, block transfer) *Transfer data size that can be selected from 8, 16, and 32 bits
6. Bit Search Module (Used by REALOS)
Searches for the position of the first bit varying between 1 and 0 in the MSB of a word
7. 16-bit Reload Timer (Including One Channel for REALOS)
*16-bit timer; 3 channels *Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32
8. UART
*Full-duplex double buffer *5 channels *Parity or no parity can be selected. *Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. *Built-in timer for dedicated baud rates *An external clock can be used as the transfer clock. *Plentiful error detection functions (parity, frame, overrun)
9. I2C Interface*
*4 channels (bridge function and pin function for 5 channels) *Master/slave transmission and reception *Clock synchronization function *Transfer direction detection function *Bus error detection function *Supports standard mode (Max 100 Kbps) and high-speed mode (Max 400 Kbps) . *Built-in FIFO function : each 16-byte sending/receiving *Arbitration function *Slave address/general call address detection function *Start condition repetitious occurrence and detection function *10-bit/7-bit slave address
10.Interrupt Controller
*Total of 17 external interrupts (one unmaskable interrupt pin (NMI) and 16 regular interrupt pins (INT15 to INT0) ) *Interrupts from internal peripherals *Priority level can be defined as programmable (16 levels) except for the unmaskable interrupt pin. *Can be used for wake-up during stop.
11.10-bit A/D Converter
*10-bit resolution, 10 channels *Sequential comparison and conversion type (conversion time : about 8.18 s) *Conversion modes (single conversion mode and scan conversion mode) *Causes of startup (software and external triggers) 3
MB91305
12. PPG
* 4 channels * 16-bit data register with 16-bit down counter and cycle setting buffer * Internal clock : Frequency-divide-by number selectable from 1, 4, 16, and 64
13. PWC
* 1 channel (1 input) * 16-bit up counter * Simple Low-pass digital filter
14. 16-bit Free-run Timer
* 16-bit 1channel * Input capture 4 channels
15. USB Function (Enabling/Disabling Function Can Be Selected by Mode Pin)
* USB2.0 full-speed, double buffer * Configuration of FIFO for End point CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN
16. Other Interval Timers
Watchdog timer
17. I/O Ports
Maximum of 98 ports
18. Other Features
* * * * * * * * * Has a built-in oscillation circuit as a clock source. INIT is provided as a reset pin. Additionally, a watchdog timer reset and software resets are provided. Stop mode and sleep mode supported as low-power consumption modes Gear function Built-in timebase timer Package : LQFP-176, 0.5 mm pitch, and 24 mm x 24 mm CMOS technology : 0.18 m Power supply voltage : two sources (0.18 m) of 3.3 V (-0.3 V to +0.3 V) and 1.8 V (-0.15 V to +0.15 V)
* : LICENSE Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
4
MB91305
PIN ASSIGNMENT
(TOP VIEW)
D23/P27 D22/P26 D21/P25 D20/P24 D19/P23 D18/P22 D17/P21 D16/P20 VDDI VSS VDDE PE2/DEOP2/TRG3 PE1/DACK2/TRG2 PE0/DREQ2/TRG1 PD5/DEOP1/TIN2 PD4/DACK1/TIN1 PD3/DREQ1/TIN0 PD2/DEOP0 PD1/DACK0 PD0/DREQ0 PC7/RIN/IORD PC6/TOUT2/IOWR PC5/TOUT1 PC4/TOUT0/TRG0 PC3/PPG3 PC2/PPG2 PC1/PPG1 PC0/PPG0 VDDI VSS UDM UDP VDDE PB7/INT15/ICU3 PB6/INT14/ICU2 PB5/INT13/ICU1 PB4/INT12/ICU0 PB3/INT11/FRCK PB2/INT10/ATRG PB1/INT9 PB0/INT8 PA7/INT7 PA6/INT6 PA5/INT5
VDDE VSS VDDI D24 D25 D26 D27 D28 D29 D30 D31 VDDE VSS VDDI RD WR0/DQMUU WR1/DQMUL/P30 CS0/P31 CS1/P32 CS4/P33 CS5/P34 CS6/P35 CS7/P36 RDY/P37 P40/BGRNT P41/BRQ SYSCLK/P42 MCLKE/P43 MCLK/P44 P45/SRAS/LBA/AS P46/SCAS/BAA P47/SWE/WR VDDE VSS VDDI A0 A1 A2 A3 A4 A5 A6 A7 A8
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ICS2 ICS1 ICS0 AN9/PF7 AN8/PF6 AN7/PF5 AN6/PF4 AN5/PF3 AN4/PF2 AN3/PF1 AN2/PF0 AN1 AN0 AVSS AVRH AVCC MD3 MD2 MD1 MD0 INIT VDDI X1 VSS X0 VDDE A23/P57 A22/P56 A21/P55 A20/P54 A19/P53 A18/P52 A17/P51 A16/P50 VDDI VSS VDDE A15 A14 A13 A12 A11 A10 A9
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
PA4/INT4 PA3/INT3 PA2/INT2 PA1/INT1 PA0/INT0 NMI VDDI VSS VDDE P97/SDA4 P96/SCL4 P95/SDA3 P94/SCL3 P93/SDA2 P92/SCL2 P91/SDA1 P90/SCL1 P84/SDA0 P83/SCL0 P82/SCK4 P81/SOUT4 P80/SIN4 P75/SCK3 P74/SOUT3 P73/SIN3 P72/SCK2 P71/SOUT2 P70/SIN2 P65/SCK1 P64/SOUT1 P63/SIN1 P62/SCK0 P61/SOUT0 P60/SIN0 VDDI VSS VDDE TRST ICLK IBREAK ICD3 ICD2 ICD1 ICD0
(FPT-176P-M07)
5
MB91305
PIN DESCRIPTION
* Function pins Pin no. 169 to 176 4 to 11 15 16 Pin name D16 to D23 P20 to P27 D24 to D31 RD WR0 /DQMUU WR1 /DQMUL P30 CS0 18 P31 CS1 19 P32 CS4 20 P33 CS5 21 P34 CS6 22 P35 CS7 23 P36 D D D D D D I/O Type* C C H H Function External data bus bit16 to bit23. It is available in the external bus mode. Can be used as ports in 8-bit external bus mode. External data bus bit24 to bit31. It is available in the external bus mode. External bus read strobe output. This pin is enabled at external bus mode. External bus write strobe output. This pin is enabled at external bus mode. When WR is used as the write strobe, this becomes the byte-enable pin (DQMUU) . External bus write strobe output. The pin is enabled when WR1 output is enabled in the external bus mode. When WR is used as the write strobe, this becomes the byte-enable pin (DQMUL) . General-purpose input/output port. The pin is enabled when the external bus write-enable output is disabled. Chip select 0 output. This pin is enabled at external bus mode. General-purpose input/output port. This pin is enabled in the single-chip mode. Chip select 1 output. This function is enabled when chip select 1 output is enabled. General-purpose input/output port. This function is enabled when chip select 1 output is disabled. Chip select 4 output. This function is enabled when chip select 4 output is enabled. General-purpose input/output port. This function is enabled when chip select 4 output is disabled. Chip select 5 output. This function is enabled when chip select 5 output is enabled. General-purpose input/output port. This function is enabled when chip select 5 output is disabled. Chip select 6 output. This function is enabled when chip select 6 output is enabled. General-purpose input/output port. This function is enabled when chip select 6 output is disabled. Chip select 7 output. This function is enabled when chip select 7 output is enabled. General-purpose input/output port. This function is enabled when chip select 7 output is disabled. (Continued)
17
D
6
MB91305
Pin no.
Pin name RDY
I/O Type*
Function External ready input. This function is enabled when external ready input is enabled. General-purpose input/output port. This function is enabled when external ready input is disabled. Acceptance output for external bus release. Outputs "L" when the external bus is released. This function is enabled when output is enabled. General-purpose input/output port. This function is enabled when external bus release acceptance is disabled. External bus release request input. Input "1" to request release of the external bus. The function is enabled when input is enabled. General-purpose input/output port. This function is enabled when the external bus release request is disabled. System clock output. This function is enabled when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.) General-purpose input/output port. This function is enabled when system clock output is disabled. Clock enable signal for SDRAM.
24 P37
D
BGRNT 25 P40 BRQ 26 P41 D D
SYSCLK 27 P42 MCLKE 28 P43 D D
General-purpose input/output port. This function is enabled when memory clock output is disabled. Memory clock output. This function is enabled when memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep mode.) General-purpose input/output port. This function is enabled when memory clock output is disabled. Address strobe output. This function is enabled when address strobe output is enabled.
MCLK 29 P44 AS LBA SRAS P45 BAA 31 SCAS P46 D D
30
D
Address load output for burst flash memory. This function is enabled when address load output is enabled. RAS strobe single for SDRAM. General-purpose input/output port. This function is enabled when address load output is disabled. Address advance output for burst flash memory. This function is enabled when address advance output is enabled. CAS strobe signal for SDRAM. General-purpose input/output port. This function is enabled when address advance output is disabled. (Continued)
7
MB91305
Pin no.
Pin name WR
I/O Type*
Function Memory write strobe output. This function is enabled when write strobe output is enabled.
32
SWE P47
D
Write output for SDRAM. General-purpose input/output port. This function is enabled when write strobe output is disabled.
36 to 51 55 to 62 64 66 68 69 to 71 72 76, 77 78 to 85
A0 to A15 A16 to A23 P50 to P57 X0 X1 INIT MD0 to MD2 MD3 AN0, AN1 AN2 to AN9 PF0 to PF7 ICS0 to ICS2 ICD0 to ICD3 IBREAK ICLK TRST SIN0 P60
H D A B I J M F
External address bus bit0 to bit15. External address bus bit16 to bit23. Can be used as ports when external address bus is not used. Clock (oscillation) input. Clock (oscillation) output. External reset input (Reset to initialize settings) These pins set the basic operating mode. Connect VCC or VSS. These pins set the basic operating mode. Connect VCC or VSS. Analog input pin. Analog input pin. Can be used as ports when analog input pin is not used.
86 to 88 89 to 92 93 94 95
C L J D B
Status output pin for development tool. Data input/output pin for development tool. Break pin for development tool. Clock pin for development tool. Reset pin for development tool. UART0 data input pin. This input is used continuously when UART0 is performing input. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. UART0 data output pin. This function is enabled when UART0 data output is enabled. General-purpose input/output port. UART0 clock input/output pin. This function is enabled when UART0 clock output is enabled. General-purpose input/output port. (Continued)
99
D
100
SOUT0 P61
D
101
SCK0 P62
D
8
MB91305
Pin no.
Pin name
I/O Type*
Function UART1 data input pin. This input is used continuously when UART1 is performing input. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. UART1 data output pin. This function is enabled when UART1 data output is enabled. General-purpose input/output port. UART1 clock input/output pin. This function is enabled when UART1 clock output is enabled. General-purpose input/output port. UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. UART2 data output pin. This function is enabled when UART2 data output is enabled. General-purpose input/output port. UART2 clock input/output pin. This function is enabled when UART2 clock output is enabled. General-purpose input/output port. UART3 data input pin. This input is used continuously when UART3 is performing input. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. UART3 data output pin. This function is enabled when UART3 data output is enabled. General-purpose input/output port. UART3 clock input/output pin. This function is enabled when UART3 clock output is enabled. General-purpose input/output port. UART4 data input pin. This input is used continuously when UART4 is performing input. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. UART4 data output pin. This function is enabled when UART4 data output is enabled. General-purpose input/output port. (Continued)
102
SIN1 P63
D
103
SOUT1 P64
D
104
SCK1 P65 SIN2 P70
D
105
D
106
SOUT2 P71
D
107
SCK2 P72 SIN3 P73
D
108
D
109
SOUT3 P74
D
110
SCK3 P75 SIN4 P80
D
111
D
112
SOUT4 P81
D
9
MB91305
Pin no.
Pin name SCK4 P82 SCL0 P83 SDA0 P84 SCL1 P90 SDA1 P91 SCL2 P92 SDA2 P93 SCL3 P94 SDA3 P95 SCL4 P96
I/O Type* D
Function UART4 clock input/output pin. This function is enabled when UART4 clock output is enabled. General-purpose input/output port. Clock I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Data I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Clock I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Data I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Clock I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Data I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Clock I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Data I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. Clock I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. (Continued)
113
114
D
115
D
116
D
117
D
118
K
119
K
120
K
121
K
122
K
10
MB91305
Pin no.
Pin name SDA4 P97
I/O Type*
Function Data I/O pin for I2C bus. This function is enabled when typical operation of I2C is enabled. The port output must remain off unless intentionally turned on. (pseudo open drain output) General-purpose input/output port. NMI (Non Maskable Interrupt) input External interrupt inputs. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. When USB function is enabled (MD3, MD2, MD1, MD0 = 0000B) , INT4 function is used only for the USB interrupt. Therefore, it is not possible to use it as an external interrupt pin. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.
123
K
127
NMI INT0 to INT3 PA0 to PA3
B
128 to 131
G
132
INT4
G
PA4 INT5 to INT7 PA5 to PA7 INT8 PB0 INT9 PB1 INT10 138 ATRG PB2 INT11 139 FRCK PB3 G G
133 to 135
G
136
G
137
G
A/D converter external trigger input. These inputs are used continuously when using as A/D start trigger. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. External clock input pin of free-run timer. These inputs are used continuously when using as external clock input pin of free-run timer. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port. (Continued)
11
MB91305
Pin no.
Pin name INT12 to INT15
I/O Type*
Function External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.
140 to 143
ICU0 to ICU3 PB4 to PB7
G
Input capture input pins. These inputs are used continuously when selected as input capture inputs. In this case, do not output to these ports unless doing so intentionally. General-purpose input/output port.
145 146
UDP UDM PPG0 to PPG3 PC0 to PC3 TOUT0
USB
+ pin of USB. - pin of USB. PPG ch.0 to PPG ch.3 timer output.
149 to 152
D General-purpose input/output port. Data output of reload timer 0. This function is enabled when data output of reload timer 0 is enabled using port function register. D External trigger input for PPG0 timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. D Data output of reload timer 1. This function is enabled when data output of reload timer 1 is enabled using port function register. General-purpose input/output port. Data output of reload timer 2. This function is enabled when data output of reload timer 2 is enabled using port function register. D Write strobe output for DMA fly-by transfer. This function is enabled when outputting a write strobe for DMA fly-by transfer is enabled. General-purpose input/output port. PWC input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. D Read strobe output for DMA fly-by transfer. This function is enabled when outputting a read strobe for DMA fly-by transfer is enabled. General-purpose input/output port. External input for DMA transfer requests. This input is used continuously when the corresponding external input for DMA transfer requests are enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. (Continued)
153
TRG0 PC4
154
TOUT1 PC5 TOUT2
155
IOWR PC6 RIN
156 IORD PC7 DREQ0 PD0
157
D
12
MB91305
Pin no.
Pin name DACK0 PD1
I/O Type* D
Function DMA external transfer request acceptance output. This function is enabled when DMA external transfer request acceptance output is enabled. General-purpose input/output port. Completion output for DMA external transfer. This function is enabled when completion output for DMA external transfer is enabled. General-purpose input/output port. External input for DMA transfer requests. This input is used continuously when external input for DMA transfer request is enabled. In this case, do not output to this port unless doing so intentionally. When using USB, this function (DMAC ch.1) cannot be used because it is used as USB data transfer. DREQ2 input is disabled. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. DMA external transfer request acceptance output. This function is enabled when DMA transfer request acceptance output is enabled. When using USB, this function (DMAC ch.1) cannot be used because it is used as USB data transfer. External transfer ACK output of DMA should be disabled. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. Completion output for DMA external transfer. This function is enabled when completion output for DMA external transfer is enabled. When using USB, this function (DMAC ch.1) cannot be used because it is used as USB data transfer. External transfer EOP output of DMA should be disabled.
158
159
DEOP0 PD2
D
DREQ1 160 TIN0 PD3 D
DACK1 161 TIN1 PD4 D
DEOP1 162 TIN2 PD5 D
Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. External input for DMA transfer requests. This input is used continuously when external input for DMA transfer request is enabled. In this case, do not output to this port unless doing so intentionally. When using USB, this function (DMAC ch.2) cannot be used because it is used as USB data transfer. DREQ2 input is disabled. External trigger input for PPG1 timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. (Continued)
DREQ2 163 TRG1 PE0 D
13
MB91305
(Continued) Pin no. Pin name I/O Type* Function DMA external transfer request acceptance output. This function is enabled when DMA transfer request acceptance output is enabled. When using USB, this function (DMAC ch.2) cannot be used because it is used as USB data transfer. External transfer ACK output of DMA should be disabled. External trigger input for PPG2 timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port. Completion output for DMA external transfer. This function is enabled when completion output for DMA external transfer is enabled. When using USB, this function (DMAC ch.2) cannot be used because it is used as USB data transfer. External transfer EOP output of DMA should be disabled. External trigger input for PPG3 timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General-purpose input/output port.
DACK2 164 TRG2 PE1 D
DEOP2 165 TRG3 PE2 D
* : For I/O circuit type, refer to " I/O CIRCUIT TYPES". * Power supply and GND pins Pin no. 2, 13, 34, 53, 65, 97, 125, 147, 167 3, 14, 35, 54, 67, 98, 126, 148, 168 1, 12, 33, 52, 63, 96, 124, 144, 166 73 74 75 Pin name VSS VDDI VDDE AVCC AVRH AVSS Function GND pins. Connect all pins at the same potential. 1.8 V power supply pins. Connect all pins at the same potential. 3.3 V power supply pins. Connect all pins at the same potential. Analog power supply pin for A/D converter Reference power supply pin for A/D converter Analog GND pin for the A/D converter
14
MB91305
I/O CIRCUIT TYPES
Type
X1
Circuit
Remarks Oscillation feedback resistance approx. 1M Clock input
A
X0
Standby control * With pull-up resistor * CMOS level hysteresis input
P-ch
P-ch
B
N-ch
Digital input * CMOS level I/O * With standby control * IOL = 4 mA Digital output
P-ch
C
N-ch
Digital output
Digital input Standby control (Continued)
15
MB91305
Type
Circuit * * * *
Remarks CMOS level output CMOS level hysteresis input With standby control IOL = 4 mA
P-ch
Digital output
D
N-ch
Digital output
Digital input Standby control * CMOS level input * No standby control
P-ch
E
N-ch
Digital input * * * * * CMOS level output CMOS level hysteresis input With standby control With analog input IOL = 4 mA
P-ch
Digital output
Digital output F
N-ch
Analog input Digital input Standby control (Continued)
16
MB91305
Type
Circuit Pull-up control
P-ch P-ch
Remarks * * * * * With pull-up control CMOS level output CMOS level hysteresis input No standby control IOL = 4 mA
Digital output G Digital output
N-ch
Digital input CMOS level output
P-ch
Digital output H Digital output
N-ch
P-ch
* CMOS level hysteresis input * No standby control
I
N-ch
Digital input (Continued)
17
MB91305
Type
Circuit
Remarks * CMOS level hysteresis input * With pull-down resistor
P-ch
J
N-ch N-ch
Digital input * * * * 3 ports for I2C CMOS level hysteresis input CMOS level output With stop control
P-ch
Open-drain control
Digital output
N-ch
Digital input Control Digital input Control Open-drain control
P-ch
K
Digital output
N-ch
Digital input
P-ch
Open-drain control
Digital output
N-ch
(Continued)
18
MB91305
(Continued) Type
Circuit Pull-down control
P-ch
Remarks * CMOS I/O * With pull-down control
Digital output L Digital output
N-ch N-ch
Digital input Analog pin
P-ch
M
N-ch
Analog input
19
MB91305
HANDLING DEVICES
* Preventing a Latch-up A latch-up can occur on a CMOS IC under following conditions. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. - When a voltage higher than VDDE or VDDI or a voltage lower than VSS is applied to an input or output pin. - When a voltage higher than the rating is applied between VDDE or VDDI and VSS. * Handling of Unused Input Pins Do not leave an unused input pin open since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * Power Supply Pins If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 F be connected between VDDE or VDDI and VSS pin at circuit points close to the device as a bypass capacitor. * Quartz Oscillation Circuit Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another as possible. It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be used to increase the expectation of stable operation. Please ask the Oscillation maker to evaluate the oscillational characteristics of the crystal and this device. * Mode Pins (MD0 to MD3) In order to prevent mistakes due to noise, and sending them into test mode, connect these pins as close to VDDE and VSS pins, and at as low an impedance as possible. * Tool Reset Pins (TRST) Be sure to input the same signal as the INIT when this pin is not used for the tool. The same processing is executed for the mass product. * Power-on Immediately after power-on, be sure to apply setting initialization reset (INIT) with INIT pin. Also immediately after power-on, keep the INIT pin at the "L" level until the oscillator has reached the required oscillation stabilization wait time. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time is set to the minimum value.) * Source Oscillation Input at Power-on At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.
20
MB91305
* Precautions at Power-On/Power-Off * Precautions when turning on and off VDDI pin and VDDE pin To ensure the reliability of LSI devices, do not continuously apply only VDDE pin for about a minute when VDDI is off. When VDDE pin is changed from off to on, the power noise may make it impossible to retain the internal state of the circuit. Power-on : Supply voltage of VDDI pin analog Supply voltage of VDDE pin signal Power-off : Signal Supply voltage of VDDE pin analog Supply voltage of VDDI pin * Indeterminate Output when the Power is Turned On When turning on the power, the output pin may remain indeterminate until internal power supply becomes stable. * Clocks * Notes on using external clock When the external clock is used, in principle, supply a clock signal to the X0 pin and an opposite-phase clock signal to the X1 pin at the same time. However, in this case the STOP mode (oscillation stop mode) must not be used (This is because, in the STOP mode, the X1 pin stops at "H" output). Example of using an external clock is illustrated in the following figure. Example of using external clock (normal)
X0 X1 MB91305
The STOP mode (oscillation stop mode) cannot be used.
* Limitations * Clock controller Secure the stabilization wait time while "L" is input to INIT pin. * Bit search module Only word access is permitted for data register for detection 0 (BSD0), data register for detection 1 (BSD1), and data register for change point detection (BSDC) . * I/O port Only byte access is permitted for ports.
21
MB91305
* Low-power Consumption Mode To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8 of the TBCR, timebase counter control register) and be sure to use the following sequence : (LD1 #value_of_stanby, R0) (LD1 #_STCR, R12) STB R0, @R12 : Writing into the standby control register (STCR) LDUB @R12, R0 : STCR read for synchronous standby LDUB @R12, R0 : Dummy re-read of STCR NOP : NOP x 5 for timing adjustment NOP NOP NOP NOP * When using the monitor debugger, do not : - Set a break point within the above sequence of instructions. - Step of the instructions within the above sequence of instructions. * Prefetch When allowing prefetch in the little endian area, only word access (32-bit) should be used to access the area. Byte access and halfword access are not working properly. * Notes on using PS register PS register is processed by some instructions in advance so that exception operations as stated below may cause breaks during interruption handling routine when using debugger and may cause updates to the display contents of PS flags. In either case, this device is designed to carry out reprocessing properly after returning from such EIT events. The operations before and after EIT events are performed as prescribed in the specification. 1. The following operations may be performed when the instruction immediately followed by a DIVOV/DIVOS instruction is acceptance of a user interrupt/NMI, single-stepped, or breaks in response to an emulator menu. (1) D0 and D1 flags are updated in advance. (2) EIT handling routine (user interrupt/NMI, or emulator) is executed. (3) After returning from the EIT, a DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1) . 2. The following operations are performed if each instruction from ORCCR, STILM, MOV Ri, and PS is executed to allow an interruption while user interrupt/NMI trigger exists. (1) PS register is updated in advance. (2) EIT handling routine (user interrupt/NMI) is executed. (3) After returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1) .
22
MB91305
* Watchdog Timer Function The watchdog timer equipped in this model operates to monitor programs to ensure that they execute reset defer function within a certain period of time, and to reset the CPU if the reset defer function is not executed due to the program runaway. For that reason, once the watchdog timer function is enabled, it keeps its operation until it is reset. By way of exception, the watchdog timer automatically defers a reset under the condition where the CPU program executions are stopped. For more detail, refer to the description section of the watchdog timer function in "Hardware Manual". If the system gets out of control and the situation becomes as mentioned above, watchdog reset may not be generated. In that case, please reset (INIT) from the external INIT pin. * Note on using A/D The MB91305 has a built-in A/D converter. Do not supply a voltage higher than VDDE to the AVCC. * Software reset in synchronous mode When software reset in the synchronous mode is used, the following two conditions must be satisfied before setting the SRST bit of the STCR (standby control register) to 0. - Set the interrupt enable flag (I-Flag) to the interrupt disabled (I-Flag = 0). - Do not use NMI. * Simultaneous occurrences of software break and user interrupt/NMI If software break and user interrupt/NMI occur together, emulator debugger may: - Stop at a point other than the programmed break points. - Not reexecute properly after halting. If such failures occur, use hardware break instead of software break. When using monitor debugger, do not set any break points within the corresponding instructions. * Stepping of the RETI Instruction In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly for the corresponding interrupt process routines after the stepping. As the result of it, the main routine and low interrupt- level programs are not executed. To avoid this situation, do not step the RETI instruction. Otherwise, perform debugging by disabling the interruptions when the debug on the corresponding interrupt routines becomes unnecessary. * Operand Break Do not set the access to the areas containing the address of stack pointer as a target of data event break. * Sample Batch File for Configuration When a program is downloaded to internal RAM to execute debug, be sure to execute the following batch file after reset. #----------------------------------------------------------------------------------------------------------------------------------# Set MODR (0x7fd) = Enable In memory + 16-bit External Bus set mem/byte 0x7fd = 0x5 #-----------------------------------------------------------------------------------------------------------------------------------
23
MB91305
BLOCK DIAGRAM
FR
CPU Core
32 32
Instruction cache 4KB
Bit search Module
RAM 64KB
Bus converter
DMAC 5 channels
32 16 adapter
External bus interface SDRAM interface
USB function
Clock control Interrupt controller UART 5 channels External interrupt
I2C interface 4 channels
10-bit A/D converter 10channels
16-bit Free-run timer 1 channel
Port
PWC 1 channel
PPG 4 channels
16-bit Reload timer 3 channels
16-bit Input capture 4 channels
24
MB91305
CPU AND CONTROL UNIT
Internal Architecture The FR family is a high-performance core based on RISC architecture and advanced instructions for embedded applications.
1. Features
* RISC architecture used Basic instruction : One instruction per cycle * 32-bit architecture General-purpose register : 32 bits x 16 * 4G bytes linear memory space * Multiplier installed 32-bit by 32-bit multiplication : 5 cycles 16-bit by 16-bit multiplication : 3 cycles * Enhanced interrupt processing function Quick response speed : 6 cycles Support of multiple interrupts Level mask function : 16 levels * Enhanced instructions for I/O operations Memory-to-memory transfer instruction Bit-processing instructions * Efficient code Basic instruction word length : 16 bits * Low-power consumption Sleep and stop modes * Gear function
25
MB91305
2. Internal Architecture
The FR family CPU uses the Harvard architecture, which has separate buses for instructions and data. A 32bit16-bit bus converter is connected to the 32-bit bus (F-bus) , providing an interface between the CPU and peripheral resources. A HarvardPrinceton bus converter is connected to both the I-bus and D-bus, providing an interface between the CUP and bus controllers.
FRex CPU D-bus I-bus
32
I address I data
32
Harvard
External address
24
D address D data
32
Princeton bus converter
External date
16
32
32-bit 16-bit Bus converter
address data
32
32
16 R-bus F-bus
Peripheral resources
Internal I/O
Bus controller F-bus RAM
26
MB91305
3. Programming Model
* Programming Model 32 bits Initial value
R0 R1 XXXX XXXXH
General-purpose register
R12 R13 R14 FP R15 SP 0000 0000H
AC XXXX XXXXH
Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiply and divide registers
PC
PS
ILM
SCR
CCR
TBR
RP
SSP
USP
MDH MDL
27
MB91305
4. Registers
* General-purpose Registers 32 bits Initial value
XXXX XXXXH
R0 R1
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator in an operation or a pointer in a memory access. Of these 16 registers, the following are intended for special applications and therefore enhanced instructions are provided for them : * R13 : Virtual accumulator (AC) * R14 : Frame pointer (FP) * R15 : Stack pointer (SP) The initial value upon reset is undefined for R0 through R14 and is "00000000H" (SSP value) for R15. * PS (Program Status) The program status register (PS : Program Status) holds the program status. The PS register consists of three parts : ILM, SCR, and CCR. All undefined bits are reserved. During reading, "0" is always read. Writing is disabled.
bit31 bit20 bit16 bit10 bit8 bit7 bit0
ILM
SCR
CCR
28
MB91305
* CCR (Condition Code Register)
bit7 bit6 bit5 S bit4 I bit3 N bit2 bit1 Z V bit0 C
Initial value --00XXXXB
S : Stack flag * This bit is cleared to "0" by a reset. * Set this bit to "0" when the RETI instruction is executed. I : Interrupt enable flag This bit is cleared to "0" by a reset. N : Negative flag The initial state of this bit upon reset is undefined. Z : Zero flag The initial state of this bit upon reset is undefined. V : Overflow flag The initial state of this bit upon reset is undefined. C : Carry flag The initial state of this bit upon reset is undefined. * SCR (System Condition code Register)
bit10 bit9 D1 D0 bit8 T
Initial value XX0B
D1, D0 : Step division flag These bits hold the intermediate data obtained when step division is executed. T : Step trace trap flag This bit specifies whether the step trace trap is to be enabled. The step trace trap function is used by an emulator. When an emulator is used, this function cannot be used in a user program. * ILM (Interrupt Level Mask Register)
bit20 bit19 bit18 bit17 bit16 ILM4 ILM3 ILM2 ILM1 ILM0
Initial value 01111B
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM register is used as a level mask. This register is initialized to 15 (01111B) by a reset.
29
MB91305
* PC (Program Counter)
bit31 bit0
Initial value XXXXXXXXH
The program counter indicates the address of the instruction being executed. The initial value upon reset is undefined. * TBR (Table Base Register)
bit31 bit0
Initial value 000FFC00H
The table base register holds the first address of the vector table to be used during EIT processing. The initial value upon reset is "000FFC00H". * RP (Return Pointer)
bit31 bit0
Initial value XXXXXXXXH
The return pointer holds the return address from a subroutine. When the CALL instruction is executed, the value of the PC is transferred to the RP . When the RET instruction is executed, the contents of the RP are transferred to the PC. The initial value upon reset is undefined. * SSP (System Stack Pointer)
bit31 bit0
Initial value 00000000H
The SSP is the system stack pointer. This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is "0". The SSP can also be specified explicitly. This register is also used as a stack pointer that specifies a stack on which the contents of the PS and PC are to be saved if an EIT occurs. The initial value upon reset is "00000000H".
30
MB91305
* USP (User Stack Pointer)
bit31 bit0
Initial value XXXXXXXXH
The USP is the user stack pointer. This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is "1". The USP can also be specified explicitly. The initial value upon reset is undefined. This register cannot be used by the RETI instruction. * MDH/MDL (Multiply & Divide register)
bit31 bit0
MDH MDL
Initial value XXXXXXXXH XXXXXXXXH
MDH and MDL are the multiply and divide registers. Each register is 32 bits long. The initial value upon reset is undefined.
31
MB91305
MODE SETTINGS
For the FR family, set the operating mode using the mode pins (MD3, MD2, MD1 and MD0) and the mode register (MODR) .
1. Mode pins
Use the four mode pins (MD3, MD2, MD1, and MD0) to specify mode vector fetch. shows the specification related to the mode vector fetch. Mode pin MD3 MD2 MD1 MD0 0 0 0 0 0 1 0 0 Reset vector access area External External
Mode name External ROM mode vector External ROM mode vector
Remarks With USB. Used at 48 MHz source oscillation. Without USB. Used at 16 MHz source oscillation.
Note : The setting other than that shown is prohibited. The single-chip mode is not supported.
2. Mode Register (MODR)
* Detailed explanation of the register MODR Address 07FDH
bit23 0 bit22 0 bit21 0 bit20 0 bit19 0 bit18 ROMA bit17 WTH1 bit16 WTH0
Initial value XXXXXXXXB
Operation mode setting bit Mode data is data written to the mode register by a mode vector fetch. After setting to the mode register (MODR) is completed, perform with the operation mode according to this register. The mode register is set by all reset sources. Accordingly, user program cannot write data to the mode register. * Detailed explanation of the mode data. * In the save way of the reset vector, set the mode vector in the vector area. * Details of the mode data which sets to the mode vector is shown below.
bit31 0 bit30 0 bit29 0 bit28 0 bit27 0 bit26 ROMA bit25 WTH1 bit24 WTH0
Initial value XXXXXXXXB
Address FFFF8H
Operation mode setting bit [bit31 to bit27] Reserved bits Be sure to set "00000B" to these bits. Operation when value other than "00000B" is set cannot guarantee. [bit26] ROMA (Internal ROM enable bit) This bit sets whether to enable internal ROM areas. 32
MB91305
ROMA 0 1
Function
Remarks Internal F-bus region (40000H to 100000H) becomes access prohibited (setting disabled) .
External ROM mode * Internal F-bus region (40000H to 100000H) becomes an external region. Internal ROM mode
* : MB91305 does not contain internal ROM. Use as external ROM mode (setting ROMA = 0) . [bit25, bit24] WTH1, WTH0 (Bus width specification bit) Set the bus width specification in external bus mode. This value is set by DBW1 and DBW0 bits of ACR0 (CS0 area) in the external bus mode. WTH1 WTH0 Function Remarks 0 0 1 1 * : not supported. Note : Mode data set in mode vector must be allocated to "0x000FFFF8H" as a byte data. In the FR family, since big endian is used as byte endian, the data must be allocated to the most significant byte in bit31 to bit24 as shown below.
bit31 bit24 bit23 bit16 bit15 bit8 bit7 bit0
0 1 0 1
8-bit bus width 16-bit bus width 32-bit bus width Single-chip mode *
External bus mode External bus mode External bus mode (setting disabled) Single-chip mode (setting disabled)
Address 0x000FFFF8H 0x000FFFFCH
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reset Vector
33
MB91305
MEMORY SPACE
1. Memory Space
The FR family has a logical address space of 4G bytes (232 addresses) , which the CPU accesses linearly. * Direct addressing area The areas in the address space listed below are used for input-output. These areas are called the direct addressing area. The address of an operand can be directly specified in an instruction. The size of the direct addressing area varies according to the size of data to be accessed : * Byte data access : 000H to 0FFH * Halfword data access : 000H to 1FFH * Word data access : 000H to 3FFH
2. Memory Map
External ROM External bus mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 0000H 0004 0000H 0005 0000H 0006 0000H 0007 0000H
Access disallowed
Direct addressing area See "3. I/O MAP"
Built-in RAM
Access disallowed
External area USB function
Fixed in the CS2 area
External area
FFFF FFFFH
Note : Internal RAM area of the MB91305 is "0003 0000H" to "0003 FFFFH".
34
MB91305
I/O MAP
Shows the correspondence between the memory space area and the peripheral resource registers. Reading the table Address 000000H Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port Data Register
Read/write attribute Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 2...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : The initial value of bits in a register are indicated as follows : "1" : Initial value "1" "0" : Initial value "0" "X" : Initial value "X" "-" : A physical register does not exist at the location.
35
MB91305
Address 000000H to 00000FH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H
Register +0 PDR0[R/W] XXXXXXXX PDR4[R/W] XXXXXXXX PDR8[R/W] XXXXXXXX PDRC[R/W] XXXXXXXX ADCTH[R/W] XXXXXX00 +1 PDR1[R/W] XXXXXXXX PDR5[R/W] XXXXXXXX PDR9[R/W] XXXXXXXX PDRD[R/W] --XXXXXX ADCTL[R/W] 00000X00 +2 PDR2[R/W] XXXXXXXX PDR6[R/W] --XXXXXX PDRA[R/W] -----XXX PDRE[R/W] -----XXX +3 PDR3[R/W] XXXXXXXX PDR7[R/W] --XXXXXX PDRB[R/W] XXXXXXXX PDRF[R/W] XXXXXXXX
Block
Reserved
R-bus Port Data Register
ADCH[R/W] 00000000 00000000 ADAT1[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 ADAT9[R] XXXXXX00 00000000 ELVR0 [R/W] 00000000 TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] ----0000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] ----0000 00000000 Reserved External interrupt DLYI/I-unit 10-bit A/D converter
ADAT0[R] XXXXXX00 00000000 ADAT2[R] XXXXXX00 00000000 ADAT4[R] XXXXXX00 00000000 ADAT6[R] XXXXXX00 00000000 ADAT8[R] XXXXXX00 00000000 TEST [R/W] 00000000 HEIRR0 [R/W] 00000000 DICR [R/W] -------0 ENIR0 [R/W] 00000000 HRCL [R/W] 0--11111
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX
16-bit Reload Timer 0
16-bit Reload Timer 1 (Continued)
36
MB91305
Address 000058H 00005CH
Register +0 +1 +2 +3 TMRLR2 [W] XXXXXXXX XXXXXXXX SSR0 [R/W] 00001000 SIDR0 [R]/ SODR0 [W] XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] ----0000 00000000 SCR0 [R/W] 00000100 DRCL0 [W] -------SCR1 [R/W] 00000100 DRCL1 [W] -------SCR2 [R/W] 00000100 DRCL2 [W] -------SCR3 [R/W] 00000100 DRCL3 [W] -------SCR4 [R/W] 00000100 DRCL4 [W] ------- PWCCH[R/W] 00-00000 SMR0 [R/W] 00--0-0UTIMC0 [R/W] 0--00001 SMR1 [R/W] 00--0-0UTIMC1 [R/W] 0--00001 SMR2 [R/W] 00--0-0UTIMC2 [R/W] 0--00001 SMR3 [R/W] 00--0-0UTIMC3 [R/W] 0--00001 SMR4 [R/W] 00--0-0UTIMC4 [R/W] 0--00001
Block
16-bit Reload Timer 2
000060H
UART0
000064H
UTIM0 [R] (UTIMR0 [W]) 00000000 00000000 SSR1 [R/W] 00001000 SIDR1 [R]/ SODR1 [W] XXXXXXXX
U-TIMER 0
000068H
UART1
00006CH
UTIM1 [R] (UTIMR1 [W]) 00000000 00000000 SSR2 [R/W] 00001000 SIDR2 [R]/ SODR2 [W] XXXXXXXX
U-TIMER 1
000070H
UART2
000074H
UTIM2 [R] (UTIMR2 [W]) 00000000 00000000 SSR3 [R/W] 00001000 SIDR3 [R]/ SODR3 [W] XXXXXXXX
U-TIMER 2
000078H
UART3
00007CH
UTIM3 [R] (UTIMR3 [W]) 00000000 00000000 SSR4 [R/W] 00001000 SIDR4 [R]/ SODR4 [W] XXXXXXXX
U-TIMER 3
000080H
UART4
000084H 000088H 00008CH 000090H 000094H 000098H 00009CH
UTIM4 [R] (UTIMR4 [W]) 00000000 00000000 PWCCL[R/W] 0000--00
U-TIMER 4 Reserved
PWCD[R] XXXXXXXX XXXXXXXX PWCC2[R/W] 000----Reserved
PWC (Continued)
PWCUD[R] XXXXXXXX XXXXXXXX
37
MB91305
Address 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H
Register +0 IFN0 [R] 00000000 IBCR0 [R/W] 00000000 IFRN0 [R/W] 00000000 IBSR0 [R] 00000000 IFCR0 [R/W] 00-00000 +1 +2 IFDR0 [R/W] 00000000 +3
Block
Reserved
ITBA0 [R, R/W] 00000000 00000000 ISMK0 [R/W] 01111111 ICCR0 [R/W] 00011111 IFCR1 [R/W] 00-00000 ISBA0 [R/W] 00000000 IFDR1 [R/W] 00000000
ITMK0 [R/W] 00111111 11111111 IFN1 [R] 00000000 IBCR1 [R/W] 00000000 IDAR0 [R/W] 00000000 IFRN1 [R/W] 00000000 IBSR1 [R] 00000000
I2C interface ch.0
ITBA1 [R, R/W] 00000000 00000000 ISMK1 [R/W] 01111111 ICCR1 [R/W] 00011111 IFCR2 [R/W] 00-00000 ISBA1 [R/W] 00000000 IFDR2 [R/W] 00000000
ITMK1 [R/W] 00111111 11111111 IFN2 [R] 00000000 IBCR2 [R/W] 00000000 IDAR1 [R/W] 00000000 IFRN2 [R/W] 00000000 IBSR2 [R] 00000000
I2C interface ch.1
ITBA2 [R, R/W] 00000000 00000000 ISMK2 [R/W] 01111111 ICCR2 [R/W] 00011111 IFCR3 [R/W] 00-00000 ISBA2 [R/W] 00000000 IFDR3 [R/W] 00000000
ITMK2 [R/W] 00111111 11111111 IFN3 [R] 00000000 IBCR3 [R/W] 00000000 IDA2R [R/W] 00000000 IFRN3 [R/W] 00000000 IBSR3 [R] 00000000
I2C interface ch.2
ITBA3 [R, R/W] 00000000 00000000 ISMK3 [R/W] 01111111 ICCR3 [R/W] 00011111 ISBA3 [R/W] 00000000 TCCS [R/W] 00000000
ITMK3 [R/W] 00111111 11111111 IDAR3 [R/W] 00000000
I2C interface ch.3
Reserved 16-bit free-run timer (Continued)
TCDT [R/W] 00000000 00000000
38
MB91305
Address 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H to 00011FH 000120H 000124H 000128H 00012CH 000130H 00134H 000138H 00013CH 000140H to 0001FCH 000200H 000204H
Register +0 +1 +2 +3 IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX EIRR1 [R/W] 00000000 PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 00000000 00000000 ICS23 [R/W] 00000000 ENIR1 [R/W] 00000000 IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX ICS01 [R/W] 00000000
Block
16-bit input capture
Reserved
ELVR1 [R/W] 00000000 00000000 PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 00000000 PCNL0 [R/W] 00000000
External interrupt
Reserved
PPG0
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 00000000 PCNL1 [R/W] 00000000
PPG1
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 00000000 PCNL2 [R/W] 00000000
PPG2
PCSR3[W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 00000000 PCNL3 [R/W] 00000000
PPG3
Reserved
DMAC
(Continued)
39
MB91305
Address 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 0002FCH 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003ECH
Register +0 +1 +2 +3 DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX ISIZE[R/W] ------10 ICHCR[R/W] 0-000000
Block
DMAC
Reserved
I-Cache
Reserved
I-Cache
Reserved (Continued)
40
MB91305
Address 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H
Register +0 +1 +2 +3 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR4 [R/W] 00000000 DDR8 [R/W] ---00000 DDRC [R/W] 00000000 PFR0 [R/W] 0--00000 PFR4 [R/W] -----000 PFRC [R/W] 1111--11 DDR5 [R/W] 00000000 DDR9 [R/W] 00000000 DDRD [R/W] --000000 PFR1 [R/W] 00000000 PFR5 [R/W] 11111111 PFR9 [R/W] 11111111 PFRD [R/W] ---101- ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR02[R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 DDR2 [R/W] 00000000 DDR6 [R/W] --000000 DDRA [R/W] 00000000 DDRE [R/W] ------00 PFR2 [R/W] 000---00 PFR6 [R/W] 00000000 PCRA [R/W] 00000000 DDR3 [R/W] ----0000 DDR7 [R/W] --000000 DDRB [R/W] 00000000 DDRF [R/W] 00000000 PFR3 [R/W] ----0000 PFR7 [R/W] -----000 PFRB [R/W] 00011-0PCRB [R/W] 00000000
Block
Bit Search Module
R-bus Port Direction Register
000414H 000418H 00041CH 000420H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H
R-bus Port Function Register
Reserved
Interrupt Controller
(Continued) 41
MB91305
Address 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH 000490H 000494H to 0005FCH 000600H to 00063FH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H
Register +0 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 +1 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 RSRR [R/W] 10000000 *2 CLKR [R/W] 00000000 *1 STCR [R/W] 00110011 *2 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00 *1 DIVR0 [R/W] 00000011 *1 CTBR [W] XXXXXXXX DIVR1[R/W] 00000000 *1 +2 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 +3 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111
Block
Interrupt Controller
Reserved
Clock Control
Reserved
ASR0 [R/W] 00000000 00000000 *1 ASR1 [R/W] XXXXXXXX XXXXXXXX *1 ASR2 [R/W] XXXXXXXX XXXXXXXX *1 ASR3 [R/W] XXXXXXXX XXXXXXXX *1 ASR4 [R/W] XXXXXXXX XXXXXXXX *1 ASR5 [R/W] XXXXXXXX XXXXXXXX *1 ASR6 [R/W] XXXXXXXX XXXXXXXX *1 ACR0 [R/W] 1111XX00 00000000 *1 ACR1 [R/W] XXXXXXXX XXXXXXXX *1 ACR2 [R/W] XXXXXXXX XXXXXXXX *1 ACR3 [R/W] XXXXXXXX XXXXXXXX *1 ACR4 [R/W] XXXXXXXX XXXXXXXX *1 ACR5 [R/W] XXXXXXXX XXXXXXXX *1 ACR6 [R/W] XXXXXXXX XXXXXXXX *1 (Continued) T-unit
42
MB91305
Address 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H
Register +0 +1 +2 +3 ASR7 [R/W] XXXXXXXX XXXXXXXX *1 AWR0 [R/W] 01111111 11111111 *1 AWR2 [R/W] XXXXXXXX XXXXXXXX *1 AWR4 [R/W] XXXXXXXX XXXXXXXX *1 AWR6 [R/W] XXXXXXXX XXXXXXXX *1 MCRA [R/W] XXXXXXXX IOWR0 [R/W] XXXXXXXX CSER [R/W] 00000001 MCRB [R/W] XXXXXXXX IOWR1 [R/W] XXXXXXXX CHER [R/W] 11111111 MODR [W] XXXXXXXX ESTS0 [R/W] X0000000 ECTL0 [R/W] 0X000000 ECNT0 [W] XXXXXXXX ESTS1 [R/W] XXXXXXXX ECTL1 [R/W] 00000000 ECNT1 [W] XXXXXXXX ESTS2 [R] 1XXXXXXX ECTL2 [W] 000X0000 EUSA [W] XXX00000 EDTR1 [W] XXXXXXXX XXXXXXXX ECTL3 [R/W] 00X00X11 EDTC [W] 0000XXXX TCR [R/W] 00000000 IOWR2 [R/W] XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX *1 AWR1 [R/W] XXXXXXXX XXXXXXXX *1 AWR3 [R/W] XXXXXXXX XXXXXXXX *1 AWR5 [R/W] XXXXXXXX XXXXXXXX *1 AWR7 [R/W] XXXXXXXX XXXXXXXX *1
Block
T-unit
RCR [R/W] 00XXXXXX XXXX0XXX
Reserved Reserved
DSU
EWP1 [R] 00000000 00000000 EDTR0 [W] XXXXXXXX XXXXXXXX
(Continued)
43
MB91305
Address 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H
Register +0 +1 EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX +2 +3
Block
DSU
(Continued)
44
MB91305
(Continued) Address 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 007104H Register +0 +1 +2 +3 EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved Block
DSU
Reserved
DMAC
*1 : Register whose initial value depends on the reset level. The registers at the INIT level are indicated. *2 : Register whose initial value depends on the reset level. The registers at the INIT level due to the INIT pin are indicated.
45
MB91305
Address 00060000H 00060004H 00060008H 0006000CH to 0006001FH 00060020H 00060024H 00060028H 0006002CH 00060030H 00060034H 00060038H 0006003CH 00060040H 00060044H 00060048H to 0006005FH 00060060H 00060064H 00060068H 0006006CH
Register +0 +1 +2 +3 FIFO0o [R] XXXXXXXX XXXXXXXX FIFO1 [R] XXXXXXXX XXXXXXXX FIFO3 [R] XXXXXXXX XXXXXXXX CONT2 [R/W] XXXXXXXX XXX00000 CONT4 [R/W] XXXXXXXX XXX00000 CONT6 [R/W] XXXXXXXX XXXX00XX CONT8 [R/W] XXXXXXXX XXX00000 CONT10 [R/W] 00000000 X00000XX TRSIZE [R/W] 00010001 00010001 RSIZE0 [R] XXXXXXXX XXXX0000 RSIZE1 [R] XXXXXXXX X0000000 ST2 [R] XXXXXXXX XXX00000 ST4 [R/W] XXXXX000 00000000 ST3 [R/W] XXXXXXXX XXX00000 ST5 [R/W] XXXX0XXX XX000000 ST1 [R/W] XXXXXX00 00000000 CONT1 [R/W] 000XX0XX XXX00000 CONT3 [R/W] XXXXXXXX XXX00000 CONT5 [R/W] XXXXXXXX XXXX00XX CONT7 [R/W] XXXXXXXX XXX00000 CONT9 [R/W] 0XX0XXXX 0XXX0000 TTSIZE [R/W] 00010001 00010001 FIFO0i [W] XXXXXXXX XXXXXXXX FIFO2 [W] XXXXXXXX XXXXXXXX -
Block
USB Function
(Continued)
46
MB91305
(Continued) Address 00060070H to 0006007FH 00060080H to 0006FFFBH 0006FFFCH Register +0 +1 +2 +3 Block
USB Function
USBRST -0-----
Reserved
USB reset
47
MB91305
INTERRUPT SOURCE TABLE
Interrupt number Interrupt source Reset Mode vector Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system No-coprocessor trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 (USB-function) External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 (Reception completed) UART1 (Reception completed) UART2 (Reception completed) UART0 (Transmission completed) UART1 (Transmission completed) Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H Address of TBR default 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H Resource number 8 9 10 0 1 2 3 4 (Continued) 48
MB91305
Interrupt number Interrupt source UART2 (Transmission completed) DMAC0 (end or error) DMAC1 (end or error) DMAC2 (end or error) DMAC3 (end or error) DMAC4 (end or error) A/D PPG0 PPG1 PPG2 PPG3 PWC External interrupt 8/U-TIMER0 External interrupt 9/U-TIMER1 External interrupt 10/U-TIMER2 Timebase timer overflow / U-TIMER3 External interrupt 11/U-TIMER4 16-bit free-run timer I2C ch.0 I C ch.1 I C ch.2 I2C ch.3 UART3 (Reception completed) UART4 (Reception completed) UART3 (Transmission completed) UART4 (Transmission completed) External interrupt 12/Input capture 0 External interrupt 13/Input capture 1 External interrupt 14/Input capture 2 External interrupt 15/Input capture 3 Reserved for system Delayed interrupt source bit
2 2
Decimal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Hexadecimal 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Interrupt level ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
Address of TBR default 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
Resource number 5 (Continued)
49
MB91305
(Continued) Interrupt number Interrupt source Reserved for system (used by REALOS) Reserved for system (used by REALOS) Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Used in INT instruction Decimal 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 Hexadecimal 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset Address of TBR default 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H Resource number
2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H
50
MB91305
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Power supply voltage*1 Power supply voltage (Internal) *1 Analog power supply voltage* Analog reference voltage* Input voltage*1 Analog pin input voltage*1 Output voltage*
1 1 1
Symbol VDDE VDDI AVCC AVRH VI VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD Ta TSTG
Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.3 VSS - 0.3 VSS - 0.3 -10 Max VSS + 4.0 VSS + 2.2 VSS + 4.0 VSS + 4.0 VDDE + 0.3 AVCC + 0.3 AVCC + 0.3 10 4 100 50 -10 -4 -50 -20 750 +70 +150
Unit V V V V V V V mA mA mA mA mA mA mA mA mW C C
Remarks *2 *2 *3 *3
"L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
*4 *5 *6 *4 *5 *6
*1 : This parameter is based on AVSS = VSS = 0.0 V. *2 : VDDE must not be lower than VSS - 0.3 V. *3 : Be careful not to exceed VDDE + 0.3 V, for example, when power is turned on. *4 : Maximum output current determines the peak value of any one of corresponding pins. *5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
51
MB91305
2. Recommended Operating Conditions
(VSS = AVSS = 0 V) Parameter Power supply voltage Analog power supply voltage Analog reference voltage Operating temperature Symbol VDDE VDDI AVCC AVRH Ta Value Min 3.0 1.65 VSS - 0.3 AVSS - 10 Max 3.6 1.95 VSS + 3.6 AVCC +70 Unit V V V V C Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
52
MB91305
3. DC Characteristics
(1) CPU (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Symbol VIH "H" level input voltage VHIS VIL "L" level input voltage "H" level output voltage "L" level output voltage Input leak current (High-Z output Leakage current) Pull-up resistance Pull-down resistance VILS Pin D31 to D16 Input ports except for D31 to D16 D31 to D16 Input ports except for D31 to D16 All output pins All output pins Conditions VDDE = 3.0 V IOH = -4.0 mA VDDE = 3.0 V IOL = 4.0 mA VDDE = 3.6 V 0.45 V < VI < VDDE VDDE = 3.6 V VI = 0.45 V VDDE = 3.6 V VI = 3.3 V fC = 16.5 MHz VDDE = 3.3 V VDDI = 1.8 V VDDE, VDDI fC = 16.5 MHz VDDE = 3.3 V VDDI = 1.8 V Ta = +25 C VDDE = 3.3 V VDDI = 1.8 V Other than VDDE, VSS AVCC and AVSS Value Min 0.7 x VDDE 0.8 x VDDE VSS VSS VDDE - 0.5 VSS Typ Max VDDE + 0.3 VDDE + 0.3 0.25 x VDDE 0.2 x VDDE VDDE 0.4 Unit V V V V Hysteresis input Hysteresis input Remarks
VOH VOL
V V
ILI
All input pins
-5
+5
A
RUP RDOWN
*1 *2
12 12
25 25
100 100
k k (Multiply by 4) When mA operating at 66 MHz mA at sleep
ICC
120
180
Power supply current
ICCS
60
90
ICCH
200
1000
A
at stop
Input capacitance
CIH
10
pF
*1 : Pins that the I/O circuit type is B and G *2 : Pins that the I/O circuit type is J
53
MB91305
(2) USB [1] DC characteristics (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter "H" level output voltage "L" level output voltage "H" level output voltage Symbol VOH VOL Pin IOH IOL IOS ILZ Conditions IOH = -100 A IOL = 100 A Full Speed VOH = VDDE - 0.4 V Low Speed VOH = VDDE - 0.4 V Full Speed VOL = 0.4 V Low Speed VOL = 0.4 V Value Min VDDE - 0.2 0 -20 -6 20 6 Typ Max VDDE 0.2 mA mA 300 5 mA A *1 *2 Unit V V Remarks
"L" level output voltage Output ShortCircuit Current Input leak current
*1 : < Output Short Circuit Current IOS > The output short circuit current IOS is the maximum current that flows when the output pin is connected to VDDE or VSS pin (within the maximum rating) . Output Short Circuit Current : The output short circuit current's value is the short-circuit current value of one terminal in one side of the differential output terminal. As this USB I/O buffer is a differential output, consider both of the pins. "H" level "H" output Monitor short circuit current
Short-circuit to GND level
3-State Enable "L"
Short-circuit to VDDE level "L" level "L" output
Monitor short circuit current
3-State Enable "L"
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MB91305
*2 : < Z leak current ILZ measurement > The leak current when VDDE or VSS potential is impressed to bi-directional pin at high-impedance state of USB I/O buffer is the input leak current ILZ. Monitor leak current Z output Impressed 0 V, VDDE level to output pin
3-State Enable "H"
55
MB91305
[2] DC Characteristics Conform to USB Specification Revision 1.1 (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Value Parameter Symbol Unit Remarks Min Max High (driven) Input Levels Low Differential Input Sensitivity Common Mode Range Low Output Levels High (driven) Differential Output Signal Voltage Bus Pull-Up Resistor on Upstream Port Terminations Bus Pull-Down Resistor on Downstream Port Termination Voltage for Upstream Port Pull-Up *1 : < Input Levels VIH and VIL > The switching-threshold voltage of the single-end-receiver in USB I/O buffer is set within the following range; VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). And, to fall the noise sensitivity, a little hysteresis is set. VIH VIL VDI VCM VOL VOH VCRS RPU RPD VTERM 2.0 0.2 0.8 0.0 2.8 1.3 1.425 1.425 3.0 0.8 2.5 0.3 3.6 2.0 1.575 1.575 3.6 V V V V V V V k k V *1 *1 *2 *2 *3 *3 *4 1.5 k 5% 1.5 k 5% *5
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MB91305
*2 : < Input Levels VDI and VCM > Reception of the USB differential data signal uses the differential-receiver. The differential input sensitivity of the differential-receiver is 200 mV, when the difference voltage between the differrential data input and local ground reference level is the following ranges; 0.8 V to 2.5 V. The voltage range above is called the common2 mode input voltage range.
1.0
Minimum differential input sensitivity (V)
0.2
0.8
2.5
Common mode input voltage (V)
*3 : < Output Levels VOL and VOH > The driver's output driving ability is set to following; - at low state (VOL) : less than 0.3 V (vs. 3.6 V, 1.5 k load) - at high state (VOH) : more than 2.8 V (vs. ground, 1.5 k load) *4 : < Output Levels VCRS > The cross voltage of the external differrencial output signal (D+/D-) in USB buffer is from 1.3 V to 2.0 V.
D+ Max 2.0 V
VCRS standard range
Min 1.3 V D-
*5 : < Terminations VTERM > Pull-up voltage for the upstream port is shown.
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MB91305
4. AC Characteristics
(1) Clock timing ratings (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Clock frequency (3) Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Symbol fC tC fC fC tC PWH PWL tCR tCF fCP fCPP fCPT tCP Internal operating clock cycle time tCPP tCPT *1 : This value is as follows; - With USB function (MD pin = 0000B) Pin X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 Conditions Value Min 37.5 12.5 10 10 40 16 3.125*2 3.125*2 3.125* 15.6 31.2 31.2
2
Max 48 16 20.8 62.5 50 50 100 8 64 32 32 1280*
2
Unit MHz MHz ns ns MHz MHz ns ns ns MHz MHz MHz ns ns ns
Remarks
Using PLL*1
Self-oscillation (1/2 division input)
At external clock
tCR + tCF CPU Peripheral External bus CPU Peripheral External bus
1280*2 1280*2
: 37.5 MHz to 48 MHz And using USB: fixed to 48 MHz (operation at a maximum internal speed of 64 MHz by quadrupling a self-oscillation frequency of 48 MHz via PLL of divided by 3.) - Without USB function (MD pin = 0010B) : 12.5 MHz to 16 MHz (operation at a maximum internal speed of 64 MHz by quadrupling a self-oscillation frequency of 16 MHz via PLL.)
*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillation circuit PLL and a gear ratio of 1/16. 12.5 [MHz] x 4 (multiply) x 1/16 (gear 1/16) = 3.125 [MHz]
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MB91305
* Conditions for measuring the clock timing ratings
tC
Output pin
0.8 VDDE 0.2 VDDE C = 30 pF
PWH tCF
PWL tCR
* Operation Assurance Range
VDDI [V]
Operation Assurance Range (Ta = - 10 C to + 70 C) VDDE = 3.0 V to 3.6 V fCPP is represented by the shaded area.
Power supply
1.95 1.65
0 0.3125
33
66
fCP/fCPP [MHz]
Internal clock
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MB91305
* External/internal clock setting range
[MHz] fCP , fCPT 64
Oscillation input clock Without USB fc = 16 MHz WIth USB fc = 48 MHz CPU :
Internal clock
Peripheral, External bus :
fCPP 32
16.5 4:4 2:2 1:2
CPU : Division ration for peripheral
Notes : * When the PLL is used, the external clock input must fall between 12.5 MHz and 16.5 MHz. * Set the PLL oscillation stabilization wait time longer than 500 s. * The internal clock gear setting should not exceed the relevant value in the table in (1) "Clock timing ratings".
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MB91305
(2) Clock output timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Cycle time MCLK (SYSCLK) MCLK (SYSCLK) MCLK (SYSCLK) MCLK (SYSCLK) Symbol tCYC Pin MCLK SYSCLK MCLK SYSCLK MCLK SYSCLK Conditions Value Min tCPT 1/2 x tCYC - 3 Max 1/2 x tCYC + 3 Unit ns Remarks *1
tCHCL
ns
*2
tCLCL
1/2 x tCYC - 3
1/2 x tCYC + 3
ns
*3
tCYC tCHCL tCLCH
MCLK SYSCLK
VOH VOL
VOH
*1 : tCYC is the frequency of one clock cycle after gearing. *2 : The following ratings are for the gear ratio set to 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. tCHCL = (1 / 2 x 1 / n) x tCYC - 10 *3 : The following rating are for the gear ratio set to 1.
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MB91305
(3) Reset and hardware standby input ratings (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter INIT input time (at power-on) tINTL INIT input time (other than at power-on) INIT tCP x 5 ns Symbol Pin Conditions Value Min * Max Unit Remarks
ns
* : INIT input time (at power-on) FAR resonator, ceramic oscillator : x 215 or greater recommended Crystal : x 221 or greater recommended : Power on X0/X1 period x 2
tINTL
INIT
0.2 Vcc
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MB91305
(4-1) Normal bus access read/write operation (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter CS0/CS1/CS4/CS5/ CS6/CS7 setup CS0/CS1/CS4/CS5/ CS6/CS7 hold Address setup Address hold Valid address Valid data input time WR0 , WR1 delay time WR0 , WR1 delay time WR0 , WR1 minimum pulse width Data setup WRx WRx Data hold time RD delay time RD delay time RD Valid data input time Data setup RD Time RD Data hold time RD minimum pulse width AS setup AS hold Symbol tCSLCH tCSHCH tASCH tCHAX tAVDV tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tASHCH RD MCLK/SYSCLK AS RD D31 to D16 Pin Conditions Value Min 3 3 3 3 tCYC - 3 tCYC 5 15 0 tCYC - 3 3 3 Max tCYC / 2 + 6 tCYC / 2 + 6 3/2 x tCYC - 15 6 6 6 6 tCYC - 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1 *2 Remarks
MCLK/SYSCLK CS0 to CS7 MCLK/SYSCLK A23 to A0 A23 to A0 D31 to D16 MCLK/SYSCLK WR0, WR1 WR0, WR1 WR0, WR1 D31 to D16 MCLK/SYSCLK RD
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC x the number of cycles added for the delay) to this rating. *2 : The following ratings are for the gear ratio set to 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 and 1/8 for n in the following equation. tAVDV : 3 / (2n) x tCYC - 15
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MB91305
tCYC BA1 VOH VOH VOH VOH
MCLK SYSCLK
tASLCH VOH
tASHCH
AS LBA
VOL
tCSLCH
tCSHCH VOH
CS0 to CS7
VOL
tASCH
tCHAX VOH VOL
A23 to A00
VOH VOL
tCHRL tRLRH
tCHRH
RD
VOL
VOH tRHDX tDSRH
tRLDV tAVDV
D31 to D16
VOH VOL
VOH VOL
tCHWL tWLWH
tCHWH
WR0, WR1
VOL
VOH
tWHDX tDSWH
D31 to D16
VOH VOL
VOH
write
VOL
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MB91305
(4-2) Multiplex bus access read/write operation (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Value CondiParameter Symbol Pin Unit Remarks tions Min Max D31 to D16 address setup time MCLK (SYSCLK) MCLK (SYSCLK) D31 to D16 address hold time D31 to D16 address setup time AS AS D31 to D16 address hold time tASCH 3 ns
tCHAX
MCLK/SYSCLK D31 to D16 (address)
3
tCYC / 2 + 6 tCYC + 3
ns
tASASH
tASHAX
AS D31 to D16 (address)
12 tCYC - 3
ns
*
ns
*
* : At CS RD/WR setup extension = 1 Note : Use the same rating as normal bus interface except for this rating.
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MB91305
* At CS RD/WR setup extension = 1
tCYC BA1 BA1W VOH VOH BA2 VOH BA3 VOH VOH
MCLK SYSCLK
VOH
tASLCH
tASHCH VOH
AS
VOL
tASASH tCSLCH
tASHAX
CS0 to CS7
VOL tASCH tCHAX
D31 to D16
VOH VOL
Address
VOH VOL
VIH VIL
Read data VIL
tDSRH
VIH
tRHDX VOH
tRLDV
RD
VOL
tRLRH tCHRL tCHRH
D31 to D16
VOH VOL
Address
VOH VOL
VOH VOL
Write data
tDSWH
VOH VOL
tWHDX VOH
WR0, WR1
VOL
tWLWH tCHWL VOH tCHWH
A23 to A00
VOL
Address
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MB91305
* At CS RD/WR setup extension = 0
tCYC BA1 BA2 VOH VOH BA3 VOH VOH
MCLK SYSCLK
VOH
VOL
VOH
AS
tASLCH
tASHCH
tCSLCH
CS0 to CS7
VOL tASCH tCHAX
D31 to D16
VOH VOL
Address VOL
VOH
VIH VIL
Read data
VIH VIL
tDSRH tRLDV
tRHDX VOH
RD
VOL
tRLRH tCHRL tCHRH
D31 to D16
VOH VOL
Address
VOH VOL
Write data
VOH VOL
tDSWH
tWHDX VOH
WR0, WR1
VOL
tWLWH tCHWL tCHWH
A23 to A00
VOH VOL
Address
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MB91305
(5) Ready input timings (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter RDY setup time MCLK (SYSCLK) MCLK (SYSCLK) RDY hold time Symbol Pin MCLK SYSCLK RDY MCLK SYSCLK RDY Conditions Value Min 10 Max Unit Remarks
tRDYS
ns
tRDYH
0
ns
tCYC
MCLK SYSCLK
VOL
VOH VOL
VOH
tRDYS
tRDYH
tRDYS
tRDYH
RDY with wait
VOL
VOH
VOH VOL
RDY without wait
VOH VOL
VOH VOL
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MB91305
(6) Hold timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time Symbol tCHBGL tCHBGH tXHAL BGRNT tHAHV tCYC - 10 tCYC + 10 ns Pin MCLK SYSCLK BGRNT Conditions Value Min tCYC / 2 - 6 tCYC / 2 - 6 tCYC - 10 Max tCYC / 2 + 6 tCYC / 2 + 6 tCYC + 10 Unit ns ns ns Remarks
Note : It takes one cycle or more from when BRQ is captured until BGRNT changes.
tCYC
VOH
VOH
VOH
VOH
MCLK SYSCLK
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
tXHAL VOH VOL
VOL tHAHV VOH
Each pin
High-impedance
VOL
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MB91305
(7) UART timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Serial clock cycle time SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" Pulse Width Serial clock "L" Pulse Width SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK4 SCK0 to SCK4 SOUT0 to SOUT4 SCK0 to SCK4 SIN0 to SIN4 SCK0 to SCK4 SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4 SOUT0 to SOUT4 SCK0 to SCK4 SIN0 to SIN4 SCK0 to SCK4 SIN0 to SIN4 External shift clock mode Conditions Value Min 8 tCYCP -80 Internal shift clock mode 100 60 4 tCYCP 4 tCYCP 60 60 Max +80 150 Unit ns ns ns ns ns ns ns ns ns Remarks
Notes : * Above rating is for CLK synchronous mode. * tCYCP indicates the peripheral clock cycle time.
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MB91305
* Internal shift clock mode
tSCYC VOL
SCK0 to SCK4
VOH
VOL
tSLOV
SOUT0 to SOUT4
VOH VOL
tIVSH
tSHIX VOH VOL
SIN0 to SIN4
VOH VOL
* External shift clock mode
tSLSH tSHSL
SCK0 to SCK4
VOL
VOL
VOH
VOL
tSLOV
SOUT0 to SOUT4
VOH VOL tIVSH
SIN0 to SIN4
VOH VOL
VOH VOL
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MB91305
(8) Timer clock Input Timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin TIN0 to TIN2 Conditions Value Min 2 tCYCP Max Unit ns Remarks
Note : tCYCP indicates the peripheral clock cycle time.
VIH
VIH VIL VIL
tTIWH
tTIWL
(9) Trigger Input Timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter A/D activation trigger input time Symbol tATG Pin ATRG Conditions Value Min 5 tCYCP Max Unit ns Remarks
Note : tCYCP indicates the peripheral clock cycle time.
tATG
ATRG
VIH
VIH
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MB91305
(10) DMA controller timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter DREQ Input pulse width DACK delay time Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCLIRL tCLIRH tCLIWL tCLIWH Pin DREQ0 to DREQ2 MCLK/SYSCLK DACK0 to DACK2 MCLK/SYSCLK DEOP0 to DEOP2 MCLK/SYSCLK Conditions Value Min 5 tCYC Max 6 6 6 6 6 6 6 6 Unit ns ns Remarks
DEOP delay time
ns
IORD delay time
ns
IOWR delay time
MCLK/SYSCLK
ns
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MB91305
tCYC BA1 BA2 VOH VOL VOL
MCLK SYSCLK
VOH VOL
tCLDL
tCLDH VOH
DACK0 to DACK2
VOL
tCLEL
tCLEH
DEOP0 to DEOP2
VOL
VOH
tCLIRL
tCLIRH
IORD
VOL
VOH
tCLIWL
tCLIWH
IOWR
VOL
VOH
tDRWH
DREQ0 to DREQ2
VOL
VOH
Note : The waveform of DACKx and DEOPx is the waveforms when the PFR register is set to FR30 compatible timing. When the setting is chip selection timing, The delay starts from the falling edge of MCLK/SYSCLK.
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MB91305
(11) USB interface (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Symbol Pin X0 X1 X0 Rise Time Fall Time Differential Rise and Fall Timing Matching Driver Output Resistance Tutfr Tutff Tutfrfm Tuzdrv UDP/ UDM UDP/ UDM UDP/ UDM UDP UDM Conditions Full Speed Full Speed Full Speed 4 4 90 28 20 20 111.11 44 ns ns % 48*1 MHz Value Min Typ Max Unit Remarks Self oscillation 2500 ppm accuracy*1 External input 2500 ppm accuracy*1 *2 *2 *2 *3
Input clock
Tucyc
Tucyc
VIH
VIH
X0
UDP
90%
90%
10%
10%
UDM
Tutfr
Tutff
*1 : AC characteristics for USB interface conform to USB Specification Revision 1.1. *2 : < Driver Characteristics Tutfr, Tutff and Tutfrfm > These are regulations of the rising / falling time of the differential data signal. This time is defined at the time between 10% to 90% of the output signal voltage. For full-speed buffer, Tutfr/Tutff is specified such that the Tutfr/Tutff ratio falls within 10% to minimize RFI radiation.
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MB91305
*3 : < Driver Characteristics ZDRV > The USB Full-speed connection is done by 90 15% of characteristic impedance (Z0). It is connected through the shielded twist 2-pair cable. In this USB standard, both following conditions must be satisfied. - The output impedance of USB Driver is from 28 to 44 . - To balance, discrete series resistor (Rs) is added. The output impedance of USB I/O Buffer of this LSI is about 3 to 19 . Therefore, it is necessary to add the series resistance Rs of 25 to 30 (recommended value 27 ).
Rs TxD+
28 to 44 Equiv. Imped.
Rs TxD- 28 to 44 Equiv. Imped.
3-State
Driver output impedance 3 to 19 Rs series resistance 25 to 30 Resistance Rs of recommended value 27 should be added.
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MB91305
(12) I2C Timing In the master mode operation (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter SCL clock frequency "L" width of the SCL clock "H" width of the SCL clock Bus free time between a STOP and START condition SCL SDA output delay time Set-up time for a repeated START condition SCL SDA Hold time (repeated) START condition SDA SCL Set-up time for STOP condition SCL SDA Data input hold time (vs.SCL) Data input set-up time (vs.SCL) Symbol fSCL tLOW tHIGH tBUS Condition Standard-mode Min 0 4.7 4.0 4.7 4.7 Max 100 5 x M*1 Fast-mode*3 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*1 Unit kHz s s s ns s The first clock pulse is generated afterword. Remarks
tDLDAT
tSUSTA
R = 1 k, C = 50 pF*4
tHDSTA
4.0
0.6
s
tSUSTO
4.0 2 x M*1 250

0.6 2 x M*1 100*2

s s ns
tHDDAT tSUDAT
*1 : M = Resource clock cycle (ns) *2 : To use high-speed mode I2C bus device for standard mode I2C bus system, it must satisfy the request condition (tSUDAT = 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output to the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + tSUDATA). *3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more. *4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.
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MB91305
In the slave mode operation (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter SCL clock frequency "L" width of the SCL clock "H" width of the SCL clock SCL SDA output delay time Bus free time between a STOP and START condition Data input hold time (vs.SCL) Data input set-up time (vs.SCL) Set-up time for a repeated START condition SCL SDA Hold time for a repeated START condition SDA SCL Set-up time for STOP condition SCL SDA Symbol fSCL tLOW tHIGH tDLDAT Condition Standard-mode Min 0 4.7 4.0 4.7 2 x M*1 250 Max 100 5 x M*1 Fast-mode*3 Min 0 1.3 0.6 1.3 2 x M*1 100*2 Max 400 5 x M*1 Unit kHz s s ns s s ns s The first clock pulse is generated afterword. Remarks
tBUS
tHDDAT tSUDAT
R = 1 k, C = 50 pF*4
tSUSTA
4.7
0.6
tHDSTA
4.0
0.6
s
tSUSTO
4.0
0.6
s
*1 : M = Resource clock cycle (ns) *2 : To use high-speed mode I2C bus device for standard mode I2C bus system, it must satisfy the request condition (tSUDAT = 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output to the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + tSUDATA). *3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more. *4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.
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MB91305
(13) SDRAM Timing (VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Output clock cycle time "H" level clock pulse width "L" level clock pulse width MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time MCLK output delay time Output hold time Data input setup time Data input hold time Symbol tCYCSD tCHSD tCLSD tODSDCKE tOHSDCKE tODSDRAS tOHSDRAS tODSDCAS tOHSDCAS tODSDWE tOHSDWE tODSDCS tOHSDCS tODSDA tOHSDA tODSDDQM tOHSDDQM tODSDD tOHSDD tISSDD tIHSDD MCLKE SRAS SCAS SWR CS6 CS7 A00 to A15 DQMUU DQMUL D16 to D31 D16 to D31 MCLK Pin Conditions Value Min 12 12 2 2 2 2 2 2 2 2 15 2 Max 32 15 15 15 15 15 15 15 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
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MB91305
tCYCSD
MCLK
VOH
VOH VOL tCHSD tCLSD VOL
VOH
MCLK
VOH tODSDCKE tODSDRAS tODSDCAS tODSDWE tODSDCS tODSDA tODSDDQM
VOH
MCLKE SRAS SCAS SWR CS6 CS7 A00 to A15 DQMUU DQMUL
VOH tOHSDCKE tOHSDRAS tOHSDCAS tOHSDWE tOHSDCS tOHSDA tOHSDDQM
VOH
tODSDD
D16 to D31
tOHSDD
VOH VOL
VOH VOL
D16 to D31
VIH VIL tISSDD tIHSDD
VIH VIL
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MB91305
5. Electrical Characteristics for the A/D Converter
(VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -10 C to +70 C) Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation between channels
Symbol
Pin AN0 to AN9 AN0 to AN9 AN0 to AN9 AN0 to AN9 AVRH AVCC AVRH AN0 to AN9
Value Min -4.0 AVRH - 5.5 8.18*1 AVSS AVSS Typ 0.1 3.6 600 Max 10 5.5 3.5 2.0 +6.0 AVRH+3.0 10 AVRH AVCC 10*2 10* 5
2
Unit BIT LSB LSB LSB LSB LSB s A V V mA A A A LSB
VOT VFST IAIN VAIN IA IAH IR IRH
*1 : For VDDI = 1.8 V 0.15 V, VDDE = AVCC = 3.3 V 0.3 V, machine clock = 32 MHz *2 : Current when A/D converter not operating (VDDE = AVCC = AVRH = 3.6 V, VDDI = 1.95 V) Notes : * The relative error increases as AVRH becomes smaller. * If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short.
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MB91305
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input circuit model
R
Analog input Comparator
C
During sampling : ON
R 4.9 k (Max) Note : The values are reference values. . * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k)
100 20
C 27 pF (Max)
(External impedance = 0 k to 20 k)
External impedance [k]
90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
External impedance [k]
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
Minimum sampling time [s]
Minimum sampling time [s]
* About the error The accuracy gets worse as | AVRH-AVSS | becomes smaller.
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MB91305
* Definition of A/D Converter Terms * Resolution Analog variation that is recognized by an A/D converter. * Linearity error The deviation between the actual conversion characteristics and a straight line connecting the device's zero transition point ("0000000000" "0000000001") and full scale transition point ("1111111110" "1111111111"). * Differential linear error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Linearity error
3FFH 3FEH
Differential linear error
Ideal characteristics
N-1
Actual conversion characteristic
Actual conversion characteristic
{1 LSB x (N-1) + VTO
Digital output
VFST
(measurement value)
Digital output
3FDH
N-2
004H 003H 002H 001H AVRL
VNT
(measurement value)
V (N-1) T
N-1
(measurement value)
Actual conversion characteristic Ideal characteristics
VNT
N-2 AVRH AVRL
(measurement value)
VTO(measurement value) Analog input
Actual conversion characteristic
AVRH
Analog input
Linear error in digital output N =
VNT - { 1LSB x (N - 1) + VOT} 1LSB V (N + 1) T - VNT [LSB] 1LSB
[LSB]
Differential linear error in digital output N = 1LSB = 1LSB' = N VOT VFST VNT VFST - VOT 1022 AVRH - AVRL 1024 [V]
[V] (Ideal value)
: A/D converter digital output value : A voltage at which digital output transitions from (000)H to (001)H. : A voltage at which digital output transitions from (3FE)H to (3FF)H. : A voltage at which digital output transitions from (N - 1) to N.
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MB91305
* Total error This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error.
Total error
3FFH 3FEH 3FDH
Actual conversion characteristic
1.5 LSB'' {1 LSB'' x (N-1) + 0.5 LSB''
Digital output
004H 003H 002H 001H AVRL
VNT
(measurement value) Actual conversion characteristic
Ideal 0.5 LSB'' characteristics
AVRH
Analog input Total error of digital output N = VNT - {1 LSB" x (N - 1) + 0.5 LSB"} [LSB] 1 LSB"
N : A/D converter digital output value VOT" (Ideal value) = AVRL + 0.5 LSB" [V] VFST" (Ideal value) = AVRH - 1.5 LSB" [V] VNT: A voltage at which digital output transitions from (N - 1) to N.
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MB91305
EXAMPLE CHARACTERISTICS
ICC-VDDI example characteristics Ta = + 25 C, fcp = 68 MHz fcpp = 34 MHz, fcpt = 34 MHz
120 100 ICC [mA] 80 60 40 20 0 1.5 1.7 1.9 VDDI [V] 2.1 120 100 ICC [mA] 80 60 40 20 0 0 10 20 30 40 50 fcp [MHz] 60 70 80
ICC-fCP example characteristics Ta = + 25 C, VDDE = 3.3 V VDDI = 1.8 V
(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)
ICCS-VDDI example characteristics Ta = + 25 C
60 ICCS [mA] 50 40 30 20 10 0 0 1.7 1.9 VDDI [V] 2.1 ICCH [A] 140 120 100 80 60 40 20 0 1.5
ICCH-VDDI example characteristics Ta = + 25 C
1.7
1.9 VDDI [V]
2.1
VOH-VDDE example characteristics Ta = + 25 C
4 3 VOH [V] 2 1 0 2 3 VDDE [V] 4 VOL [V] 0.6
VOL-VDDE example characteristics Ta = + 25 C
0.4
0.2
0 2 3 VDDE [V] 4
Note : Not including USB I/O (Continued)
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MB91305
Pull-up resistor example characteristics Ta = + 25 C
120 120
Pull-down resistor example characteristics Ta = + 25 C
R [k]
R [k]
80
80
40
40
0 2 3 VDDE [V] 4
0 2 3 VDDE [V] 4
ICC-VDDI example characteristics Ta = + 25 C, fcp = 68 MHz fcpp = 34 MHz, fcpt = 34 MHz
120 100 ICC [mA] 80 60 40 20 0 1.5 1.7 1.9 VDDI [V] 2.1 120 100 ICC [mA] 80 60 40 20 0 0 10
ICC-fCP example characteristics Ta = + 25 C, VDDE = 3.3 V VDDI = 1.8 V
20
30
40 50 fcp [MHz]
60
70
80
(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)
ICCS-VDDI example characteristics Ta = + 25 C
60 ICCS [mA] ICCH [A] 50 40 30 20 10 0 0 1.7 1.9 VDDI [V] 2.1 140 120 100 80 60 40 20 0 1.5
ICCH-VDDI example characteristics Ta = + 25 C
1.7
1.9 VDDI [V]
2.1
Note : Not including USB I/O (Continued)
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MB91305
(Continued) VOH-VDDE example characteristics Ta = + 25 C
4 3 VOH [V] 2 1 0 2 3 VDDE [V] 4 VOL [V] 0.4 0.6
VOL-VDDE example characteristics Ta = + 25 C
0.2
0 2 3 VDDE [V] 4
Pull-up resistor example characteristics Ta = + 25 C
120
Pull-down resistor example characteristics Ta = + 25 C
120
R [k]
80 R [k] 2 3 VDDE [V] 4
80
40
40
0
0 2 3 VDDE [V] 4
Note : Not including USB I/O
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MB91305
ORDERING INFORMATION
Part number MB91305PMC Package 176-pin plastic LQFP (FPT-176P-M07) Remarks
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MB91305
PACKAGE DIMENSION
176-pin plastic LQFP (FPT-176P-M07) Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25 (.010) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ 0.1450.055 (.006.002)
132 89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0~8
0.100.10 (.004.004) (Stand off)
INDEX 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
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MB91305
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept.
F0604

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